The internal receiver is an enhanced version of the miniADSB
concept. Major change is splitting up the total gain into two ERA-3 devices, so one of them is placed before the first
filter, and so improving the total noise figure by about 3dB and the sensitivity by 3.5dB. Also the whole chain is matched,
which results in a flatter passband. Last improvment is the narrowband matching of the AD8313 log detector.
This receiver was designed by Luis Cupido, CT1DMK.
The signal is then sampled into digital world using MAX1192 AD converters operating with 16MSamples/sec.
One signal is provided from the internal receiver, up to three signals from additional, preferred miniADSB,
receivers can be fed into the circuit.
The first processing in the FPGA is a signal regenerator and the preamble detector.
This stage reconstructs the manchester data signal and detects all preamples, even out of the noise.
This stage also drives the ADC and is running on 64MHz.
Behind this, three frame decoders are implemented, which start on a preamble pulse and,
depending on the settings, discard the frame or deliver it to the a 128 locations x 160 bit wide FIFO.
Due to the concept this stages just run with 1MHz, which saves a lot of power.
There are 48 bits of a MLAT counter added to each frame, so that the time of arrival is always correct,
even if the traffic cannot be sent out immediately.
The serial frame builder component then reformats the received data into hexdump,
adds the special characters that identify the frame format, and finally transmits
it as RS232 with start and stopbits towards the interface device.
Finally, there is an option of three external interface devices: For USB,
a FT232R is always installed on the board.
Optionally a Lantronix Xport or a BTM-222 Bluetooth device can become added on the bottom side of the Mode-S Beast.
The hardware handshake signal "RTS" is used to control the data flow between the interface device and the FPGA.